The present invention relates to a semiconductor device and a manufacturing technique of the semiconductor device. More particularly, the present invention relates to a technique for optimizing an amount of nitrogen that is contained in an interface between a gate insulation film and a semiconductor substrate of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), thereby improving device reliability such as hot carrier reliability.
In recent years, since it becomes evident that a gate oxide film is oxy-nitrided in gas atmosphere such as NO or N2O, and nitrogen atoms are piled up on an interface between the gate oxide film and a silicon substrate, thereby making it possible to improve a hot carrier reliability of an n-channel type MISFET, and restrain boron (B) penetration from a p-type polycrystal silicon gate, this oxynitridation has been practically available for use in logic products.
However, there has been a report that, if an amount of nitrogen in the interface between the gate oxide film and the silicon substrate (hereinafter, referred to as a SiO2/Si interface) is excessively increased, a p-channel type MISFET is severely degraded (for example, NBTI (negative bias temperature instability) described in 1999 VLSI Symposium Digest of Technical Paper, P. 73). Therefore, control of an amount of nitrogen in the above interface is an important task.
In addition, as a substitutive technique of an oxynitridation, for example, as described in Japanese Patent Application Laid-open No. 10-79506, it is known that a similar advantageous effect is attained by ion implantation when source and drain extensions are formed after nitrogen or a nitrogen-containing ion has been subjected to gate electrode processing. FIG. 84 shows the test result showing an example, where remarkable improvement of a hot carrier reliability is achieved by almost one hundred times in a nitrogen atom of 1xc3x971015 cmxe2x88x922 in dosage.
However, according to study of the Inventor, recent logic LSI products employ gate oxide films having dual oxide thickness (hereinafter, these films are referred to as a thin film and a thick film for clarity). Thus, in the same oxynitridation, as a result of shortage of an amount of nitrogen relevant to thick film, there has been a problem that a hot carrier reliability of an n-channel type MISFET using a thick film tends to be in short. On the other hand, in the case where an oxynitridation condition is determined in accordance with a thick film, there has been a problem that an excessive amount of nitrogen is produced, and the NBTI durability of the p-channel type MISFET is impaired, or alternatively, a fixed charge increases, and threshold voltages of the n-channel MISFET and p-channel MISFET are greatly shifted. This problem will be described more specifically with reference to the accompanying drawings.
FIG. 79 to FIG. 83 each show an outline of CMOS process flow using a gate oxide film having thickness of dual oxide level. A shallow trench isolation region 11 is formed on a silicon (Si) substrate (hereinafter, simply referred to as a substrate) 10, and a p-well 12 for n-channel type MISFET and an n-well 13 for p-channel type MISFET are formed. Then, the surface of a substrate 10 is fully oxidized, and a thick oxide film 14 is formed (FIG. 79). Next, the surface 10 of the thick MISFET section is covered with a resist mask 111, and a thick oxide film 14 at the thin MISFET section is removed by etching (FIG. 80). Next, after washing the surface of the substrate 10, the substrate 10 is re-oxidized, thereby forming a thin oxide film 15 on the substrate 10 of the thin MISFET section (FIG. 81). In this case, the thick oxide film 14 is thus re-oxidized so as to have desired film thickness, although the film thickness slightly decreases due to the above washing step. Thereafter, the full face of the substrate 10 is subjected to oxynitridation by employing an NO gas so that an nitrogen atom in desired amount is contained in an interface between the fate oxide film (14, 15) and the substrate 10.
Next, a polycrystal silicon film deposited on the substrate 10 is patterned, thereby forming gate electrodes 31 and 32. Thereafter, an extension region (nxe2x88x92 type semiconductor region) 113 and a halo region (p-type semiconductor region) 114 for punch-through restraining are formed at the p-well 12 of the thick MISFET section, and an extension region (p-type semiconductor region) 116 and a halo region (n-type semiconductor region) 117 are formed. In addition, an extension region (n-type semiconductor region) 119 and a halo region (p-type semiconductor region) 120 are formed at the p-well 12 of the thin MISFET section, and an extension region (pxe2x88x92 type semiconductor region) 122 and a halo region (n-type semiconductor region) 123 are formed at the n-well 13 (FIG. 82).
Next, a sidewall spacer 124 is formed on the side wall of gate electrodes 31a, 31b, 32a, and 32b, and then, an As ion and an boron fluoride ion is implanted in the substrate 10, thereby forming a n+ type semiconductor region 125 with high impurity concentration that configures the source and drain of an n-channel type MISFET and a p-channel type MISFET 126 with high impurity concentration that configures the source and drain of a p-channel type MISFET. Thereafter, a silicide layer 127 is formed each on the surface of the source and drain of the n-channel type MISFET (n+ type semiconductor region 125) and the surface of the source and drain of the p-channel type MISFET (p+ type semiconductor region 126) (FIG. 83).
However, in the above process, gate oxide films 14 and 15 of dual oxide thickness are treated in accordance with one oxynitridation step. Thus, an amount of interfacial nitrogen between the thick gate oxide film 14 and the substrate 10 is smaller than that between an interface between the thin gate oxide film 15 and the substrate 10, and a hot carrier reliability of the MISFET using a thick film becomes insufficient.
FIG. 85 shows the testing result when oxide under-layer dependency of an amount of nitrogen on the interface is investigated. In the figure, it is found that the current thick film (7 nm) contains nitrogen in amount almost 5 times as much as the current thin film (2.5 nm). Here, this phenomenon is studied by using a simple model.
When an Si substrate surface-oxide in gas such as NO is heat treated, nitridation species such as NO molecules solve and thermally diffuses in the oxide film, whereby the specifies reach an SiO2/Si interface. It is considered that this interface has a density of a site that can be coupled with nitrogen, and thus, functions as a sink. In consideration of the nitride species concentration in the oxide film based on this presumption, when the thickness of the oxide film is thin, the film has a linear distribution as shown in FIG. 86, and a flux F of the nitride specifies is prosectional to Ns/tox (Ns: oxide film surface concentration such as NO molecules (depending on solid solubility) and tox: Oxide under-layer film thickness). Therefore, the nitrogen amount N of the interface is led to be inversely prosectional to xe2x80x9ctoxxe2x80x9d by dN/dt=F. In actuality, when the oxide film becomes thick, a complimentary error function distribution as shown in FIG. 87 is obtained, and thus, the flux F decreases more remarkably than linear approximation. Therefore, in the case where an oxide film having two types of thickness is processed in one oxynitridation process, it is found that an amount of nitrogen on the thick interface is inversely prosectional to an amount of nitrogen in thin filmxc3x97film thickness at most. A policy that a thinner film is produced without changing the film thickness of the thick film is effectual, and thus, a difference in amount of nitrogen is likely to be more remarkable.
In addition, in DRAM (Dynamic Random Access Memory) embedded logic products, blanket oxynitridation is carried out while a logic side is defined as a reference, and thus, an amount of B (boron) channel implantation into a DRAM memory cell transistor increases. That is, if oxynitridation is carried out in order to improve a hot carrier reliability of a MISFET that configures the DRAM peripheral circuit, the threshold voltage of the n-channel type MISFET is reduced by generation of a fixed positive charge on the SiO2/Si interface. Thus, an amount of channel B ion implantation into the n-channel type MISFET that configures a memory cell must be increased. As a result, there occurs a DRAM specific problem that the concentration of B in the substrate increases, the xe2x80x9cpnxe2x80x9d junction electric field is intense, a leak current increases, and data retention time is reduced. This problem is more serious as a highly integrated DRAM is embedded in the future.
The present invention has been made in order to solve the foregoing problem. It is an object of the present invention to provide a technique of improving a hot carrier reliability of a MISFET having a thick gate insulation film in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film.
The foregoing and other objects and novel characteristics of the present invention would be evident from a description and accompanying drawings of the specification.
An outline of typical information disclosed in the present application is briefly described as follows. According to one aspect of the present invention, there is provided a semiconductor device comprising:
a first n channel and p channel MISFET having a first gate insulation film; and
a second n channel and p channel MISFET having a second gate insulation film that is thicker than the first MISFET, wherein nitrogen in amount equal to or greater than that determined by a reverse ratio of film thickness as compared with an amount that exists on an interface between the first gate insulation film and the semiconductor substrate is contained in at least one part of an interface between the second gate insulation film and a semiconductor substrate. Further, nitrogen in amount equal to or greater than that existing on an interface between a gate insulation film of the second p-channel MISFET and the substrate is contained in at least one part of an interface between a gate insulation film and a substrate of the second p-channel MISFET.
A semiconductor device, where an n-channel type MISFET that wherein a memory cell of a DRAM is formed in a first region of a main face of a semiconductor substrate, and an n-channel type MISFET and a p-channel type MISFET, each of which configures a peripheral circuit or a logic LSI of the DRAM, is formed in a second region of a main face of the semiconductor substrate, wherein nitrogen is contained in at least one part of an interface between a gate insulation film of an n-channel type MISFET and a p-channel type MISFET, each of which configures a peripheral circuit or a logic LSI of the DRAM.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor comprising the steps of:
(a) forming a first gate insulation film in a first region of a main face of a semiconductor substrate, followed by forming a second gate insulation film that is thicker than the first gate insulation film in a second region of a main face of the semiconductor substrate;
(b) applying oxynitridation to the first and second gate insulation film;
(c) forming a first gate electrode of a first MISFET on the top of the first gate insulation film, followed by forming a second gate electrode of a second MISFET on the top of the second insulation film; and
(d) implanting an ion that contains nitrogen or nitrogen atoms in at least one part of an interface between the second gate insulation film and the semiconductor substrate before or after the step (a) or before or after the step (c).
According to a yet another aspect of the present invention, there is a method of manufacturing a semiconductor device comprising the steps of:
(a) forming a second gate insulation film on a main face of a semiconductor substrate;
(b) applying oxynitridation to the second gate insulation film;
(c) removing the second gate insulation film in a first region of the semiconductor substrate, followed by leaving the second gate insulation film in a second region of the semiconductor substrate;
(d) oxidizing the semiconductor substrate, thereby forming a first gate insulation film that is thinner than the second gate insulation film in the first region of the semiconductor substrate;
(e) applying second oxynitridation to the first and second gate insulation films; and
(f) forming a first gate electrode of a first MISFET on the top of the first gate insulation film, followed by forming a second gate electrode of a second MISFET on the top of the second gate insulation film.